๐ฌ Design Verification Engineer ย |ย โจ๏ธ Vim Enthusiast
๐ง systemverilog.vim
SystemVerilog & UVM syntax highlighting and indent plugin for Vim/Neovim. Fixes indentation edge cases, adds UVM highlighting, and completes matchit pairs.
๐ sv_trace
Signal/variable tracing plugin for Verilog/SystemVerilog/UVM โ traces declarations, drivers and loads across your project, with hierarchy trees and Mermaid topology export.
๐ก Sparse-recovery
Sparse recovery / compressed sensing research โ paper code will be released here.
- ๐ ๅ้ Jericho+Ramon ไธ Tomahawk ๆๆฏๆถๆไธๅบๅซ่ฏฆ่งฃ โ 2026-10-18
- ๐ UVMๆฅๅฃไฟกๅทๅๆญฅๆบๅถ โ 2026-08-19
- ๐ก UVM่ฐ่ฏๅ่ฝๅ จ่งฃๆ โ 2026-08-19
- ๐ก UVM Sequence ๅญฆไน ่ฎฐๅฝ โ 2026-08-01
- ๐ Common ๅ่งฃ โ 2026-08-01
โ More at [www.sqlmaps.com](https://www.sqlmaps.com/)
- ๐ฌ Design Verification Engineer โ focused on SystemVerilog / UVM chip functional verification
- โจ๏ธ Vim power user โ writes code in Vim daily and builds plugins (
systemverilog.vim,sv_trace) - ๐ Tooling tinkerer โ from Vim config to workflow automation, I script away the boring stuff
- ๐ฑ Currently learning โ better verification methodologies & advanced editor skills
Thanks for stopping by ๐