A small, light weight, RISC CPU soft core
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Sep 16, 2026 - Verilog
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risc-cpu
Here are 13 public repositories matching this topic...
14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository.
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Dec 30, 2021 - C++
8-bit ALU lookup-table project for Logisim-evolution
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Oct 18, 2026
A collection of digital hardware components designed in SystemVerilog, including counters, registers, an 8-bit ALU, and a 4×8 register file. Built to explore RTL design, digital logic, and verification while progressing toward a simple RISC CPU implementation.
verilog systemverilog computer-architecture risc-v digital-design digital-electronics risc-cpu cpu-design rtl-design hardware-design
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Oct 28, 2026 - SystemVerilog
16-bit MIPS Processor from scratch in VHDL
asic cpu fpga mips processor vhdl mips-assembly risc hdl pipeline-processor soft-core risc-cpu custom-cpu
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Jan 24, 2024 - VHDL
Structural Verilog implementation of a pipelined RISC CPU datapath and control unit based on Mano & Kime.
verilog computer-architecture icarus-verilog testbench digital-design risc-cpu rtl-design pipelined-processor
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Apr 24, 2026 - Verilog
A 32-bit single cycle RISC CPU based on Harvard architecture with no cache or pipeline, by having very simple and reduced instruction set it can be used for educational purpose.
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Jun 22, 2022 - Verilog
4-Bit RISC CPU Datapath with 3-Stage Pipeline implemented in Verilog HDL & verified on Xilinx Virtex-7 (88/88 checks passed).
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Oct 17, 2026 - Verilog
Synthesizable 16-bit RISC CPU core designed in VHDL with an 8-bit ALU, 16 general-purpose registers, an 8-state FSM, and ModelSim testbench.
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Oct 18, 2026 - VHDL
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