Verilator open-source SystemVerilog simulator and lint system
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Oct 31, 2026 - SystemVerilog
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verilator
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RISC-V CPU Core (RV32IM)
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Sep 18, 2021 - Verilog
A small, light weight, RISC CPU soft core
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Sep 16, 2026 - Verilog
32-bit Superscalar RISC-V CPU
linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors
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Sep 18, 2021 - Verilog
VeeR EH1 core
fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer
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Jul 16, 2026 - SystemVerilog
An abstraction library for interfacing EDA tools
fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass
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Sep 15, 2026 - Python
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain
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Oct 17, 2026 - SystemVerilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface
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Aug 10, 2026 - Verilog
Verilog/SystemVerilog support for VS Code
ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls
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Oct 28, 2026 - TypeScript
A simple, basic, formally verified UART controller
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Jan 29, 2024 - Verilog
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2
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Oct 31, 2026 - SystemVerilog
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl
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Nov 25, 2019 - SystemVerilog
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
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Feb 2, 2026 - SystemVerilog
A utility for Composing FPGA designs from Peripherals
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Aug 31, 2026 - C++
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